/*-----------------------------------------------------------------------
								 \\\|///
							   \\  - -  //
								(  @ @  )  
+-----------------------------oOOo-(_)-oOOo-----------------------------+
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2012-20xx CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
Email Address 		: 		thereturnofbingo@gmail.com
Filename			:		MCU2FPGA_SPI_TB.v
Data				:		2013-02-21
Description			:		The testbench of SPI communicaton.
Modification History	:
Data			By			Version			Change Description
=========================================================================
13/02/21		CrazyBingo	1.0				Original
13/10/17		CrazyBingo	2.0				Original
-------------------------------------------------------------------------
|                                     Oooo								|
+-------------------------------oooO--(   )-----------------------------+
                               (   )   ) /
                                \ (   (_/
                                 \_)
-----------------------------------------------------------------------*/   
/***************************************************************************
	//mcu spi interface
	input			spi_cs,		//Chip select enable, default:L
	input			spi_sck	,	//Data transfer clock
	input			spi_mosi,	//Master output and slave input
	input			spi_miso,	//Master input and slave output	
***************************************************************************/

`timescale 1ns/1ns
module MCU2FPGA_SPI_TB;


//------------------------------------------
//clock generate module
reg	clk;  
reg	rst_n;
parameter PERIOD = 10;	//100MHz
initial	
begin
	clk = 0;
	forever	#(PERIOD/2)	
	clk = ~clk;
end

task task_reset;
begin
	rst_n = 0;
	repeat(2) @(negedge clk);
	rst_n = 1;
end
endtask
wire	clk_ref = clk;
wire	sys_rst_n = rst_n;

//----------------------------------------------
//the target component instantiation
reg	spi_cs;
reg	spi_sck;
reg	spi_mosi;
//-----------------------------------
wire			rxd_flag;
wire	[7:0]	rxd_data;
spi_receiver	u_spi_receiver
(
	//global clock
	.clk			(clk_ref),			//100MHz clock
	.rst_n			(sys_rst_n),		//global reset
	
	//mcu spi interface
	.spi_cs			(spi_cs),		//Chip select enable, default:L
	.spi_sck		(spi_sck),		//Data transfer clock
	.spi_mosi		(spi_mosi),		//Master output and slave input
//	.spi_miso		(spi_miso),		//Master input and slave output

	//user interface
	.rxd_flag		(rxd_flag),
	.rxd_data		(rxd_data)
);

//---------------------------------------
wire	txd_flag;
spi_transfer u_spi_transfer
(
	//global clock
	.clk			(clk_ref),			//100MHz clock
	.rst_n			(sys_rst_n),		//global reset
	
	//mcu spi interface
	.spi_cs			(spi_cs),		//Chip select enable, default:L
	.spi_sck		(spi_sck),		//Data transfer clock
//	.spi_mosi		(spi_mosi),		//Master output and slave input
	.spi_miso		(spi_miso),		//Master input and slave output

	//user interface		
	.txd_en			(rxd_flag),
	.txd_data		(rxd_data),
	.txd_flag		(txd_flag)		
);


//---------------------------------------------
//mcu spi data transfer
task task_mcu_spi_txd;
input	[7:0] mcu_data;
begin
	spi_cs = 0; #100;
	spi_sck = 0;	spi_mosi = mcu_data[7];	 #100;	spi_sck = 1; #100;	//Bit[7]
	spi_sck = 0;	spi_mosi = mcu_data[6];	 #100;	spi_sck = 1; #100;	//Bit[6]
	spi_sck = 0;	spi_mosi = mcu_data[5];	 #100;	spi_sck = 1; #100;	//Bit[5]
	spi_sck = 0;	spi_mosi = mcu_data[4];	 #100;	spi_sck = 1; #100;	//Bit[4]
	spi_sck = 0;	spi_mosi = mcu_data[3];	 #100;	spi_sck = 1; #100;	//Bit[3]
	spi_sck = 0;	spi_mosi = mcu_data[2];	 #100;	spi_sck = 1; #100;	//Bit[2]
	spi_sck = 0;	spi_mosi = mcu_data[1];	 #100;	spi_sck = 1; #100;	//Bit[1]                                                                                                                         
	spi_sck = 0;	spi_mosi = mcu_data[0];	 #100;	spi_sck = 1; #100;	//Bit[0]
	spi_cs = 1; spi_sck = 0; #100;
end
endtask


//---------------------------------------------
//system initialization
task task_sysinit;
begin
	spi_cs = 1;
	spi_sck = 0;
	spi_mosi = 0;
end
endtask


//---------------------------------------
//testbench of the RTL
initial
begin
	task_sysinit;
	task_reset;
	
	#100;	
	task_mcu_spi_txd(8'h95);
	
	#100;	
	task_mcu_spi_txd(8'hbe);
	
	#100;	
	task_mcu_spi_txd(8'hcb);	

end

endmodule

